搜索资源列表
mxuliematlab
- m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
m15
- 扩频通信M序列,编码,通用VHDL语言-M sequence spread spectrum communication, coding, generic VHDL
m_queue
- 让读者对基于VHDL可编程m序列发生器有更深的了解
M_generate
- m序列产生编码，vhdl硬件实现用于实现调制解调
PN_Generator.rar
- 用Verilog编写的一个简单的产生伪随机序列的代码（m序列），比较实用。,Verilog prepared with the emergence of a simple pseudo-random code sequence (m sequence), more practical.
m.rar
- 扩频接收机设计的部分，一个用vhdl语言编写的m序列生成器，,A language with vhdl generator sequence m
fpdpsk
- FSK/PSK信号调制器的VHDL程序，共分为分频器、m序列产生器、跳变检测、2:1数据选择器、正弦波信号产生器和DAC(数、模变换器)6部分-FSK/PSK signal modulator VHDL program is divided into divider, m sequence generator, transition detection, 2:1 data selector, the sine wave signal generator and DAC (number, mode
interweave_1
- 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by colu
m
- 基于VHDL的M序列发生器~大家可以作为参考试用看-VHDL-based M-sequence generator ~ everybody can watch the trial as a reference
2mxulie
- 基于CPLD的数字通信系统 2m序列 用VHDL产生 2m序列信号-CPLD-based digital communications systems using VHDL generate 2m sequence signal sequence 2m
m
- m序列信号发生器的设计，用于保密通信，和信息加密，属于流密码。-m sequence signal generator designed for confidential communications, and information encryption, part of stream ciphers.
m
- 由20位移位寄存器线性反馈产生的m序列的vhdl代码-20-bit shift register linear feedback sequence generated vhdl code m
FPGA-M-sequence-generator
- FPGA VHDL 语言M序列发生器，可以帮助各位需要的朋友探讨研究-FPGA VHDL language M-sequence generator, can you help a friend in need of research
vhdl--eda
- m 序列发生器 计数器 七段数码管显示 bcd 十六进制转换-failed to translate
PSK-modulator-design-using-VHDL
- 用VHDL语言编程来实现PSK调制器的设计，1）产生基带序列 ，此处用M序列 2）完成PSK调制 -PSK modulator using VHDL language programming to design, 1) generates the baseband sequence, here M-sequence 2) complete the PSK modulation
m
- 这是vhdl编写的产生7位m序列的程序，类比可以产生更多为的。而m序列即可作为输入测试信号，也可以模拟噪声。-It is written vhdl 7 m sequence generation process, can produce more for the analogy. The m-sequence can be used as an input test signal, it can simulate noise.
m_15
- vhdl m序列信号发生器 作者手写绝对原始-random m of vhdl
pseudo-random-number-VHDL
- 伪随机序列发生器的vhdl软件，有m序列和gold序列的算法-pseudo random number generator
fpga代码
- 实现了m序列产生，同步信号提取功能，实现了所有功能(The m sequence is generated and the synchronous signal extraction function is realized)
15阶m序列VHDL
- 高阶m序列，VHDL语言在ISE平台完成，生成多项式f(x)=x15+x+1